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I am currently debugging LVDS receiver on my hardware implemented by altera IP: altlvds_tx/rx. I am facing a problem. When incoming data include more than 4 or 5 successive 0, the received data would be wrong. My design contains 4 channels. The channel is different from others. Some of channel even has problem when successive 0 is only 4. Some of channels have no problem when successive 0 is 5. I simulated by modelsim, the result is correct. The hardware is a released product which I am sure there is no hardware issue. Can any help me out regarding to this issue? thanks alot.
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Without seeing the schematic and layout, we can only guess ... so here's a few:
1. You have AC coupled your LVDS link, or
2. Your frame clock is misaligned with your LVDS, possibly due to this one channel having a longer trace than the others (though this would have to be a very bad layout to get high enough skew).
3. You are getting coupling between traces, and you just happen to notice it when the other trace has zeros on it. Try toggling one trace and see what is received on all traces.
Cheers,
Dave
Honored Contributor
