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Altera_Forum
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14 years ago

altera LVDS receiver

I am currently debugging LVDS receiver on my hardware implemented by altera IP: altlvds_tx/rx. I am facing a problem. When incoming data include more than 4 or 5 successive 0, the received data would...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Assuming the link is DC coupled, the receiver bit clock may have an unsuitable alignment. I usually determine the timing margins and center the bit clock to the range.

What's your bit rate and expectable sampling window?

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Thanks FvM. Honestly I don't now what the samplng window is and don't know if it is really center alignment. I use Cyconle III device which have limited options to choose.

I use control characters for data alignment as recommended by Altera. I write a component by VHDL dedicated for data alignment. I simualted the design by modelsim, there is no issue. Could you please tell me how to check samping window/center alignment?

Thanks alot

Regards