altera LVDS receiver

--- Quote Start ---

Assuming the link is DC coupled, the receiver bit clock may have an unsuitable alignment. I usually determine the timing margins and center the bit clock to the range.

What's your bit rate and expectable sampling window?

--- Quote End ---

Thanks FvM. Honestly I don't now what the samplng window is and don't know if it is really center alignment. I use Cyconle III device which have limited options to choose.

I use control characters for data alignment as recommended by Altera. I write a component by VHDL dedicated for data alignment. I simualted the design by modelsim, there is no issue. Could you please tell me how to check samping window/center alignment?

Thanks alot

Regards