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yuriah726's avatar
yuriah726
Icon for New Contributor rankNew Contributor
3 hours ago

Agilex 5 SDI 148.5 and 148.35 MHz refclks

I'm working on a design for the Agilex 5 that is going to need to be able to switch between integer and fractional framerates, and I'm trying to figure out and understand the clocking structure involved.

In the GTS SDI II IP User Guide, there is a set of parameters for "Transceiver reference clock frequency" and "Dynamic TX clock switching" under the category "Transceiver Options", however I don't see these parameters in Quartus. Is there somewhere else that I can enable this option to have the two different reference clock frequencies? Do I need this enabled, or is there some other way that I can switch between the two frequencies?

In addition, what does the clocking structure look like to do this? Is there a way to provide 148.5 MHz to the board and then generate the 148.35 from a PLL to be multiplexed? Or do I need to provide both clock frequencies separately? If I need to provide both clock frequencies separately, what pins can I use for the 148.35 MHz reference clock? The two differential pairs of reference clocks for the GTS bank are already being used for the System PLL reference clock and the 148.5 MHz.

Any help with these questions would be greatly appreciated.

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1 Reply

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 hour ago

    Hi yuriah726 ,

    In the GTS SDI II IP User Guide, there is a set of parameters for "Transceiver reference clock frequency" and "Dynamic TX clock switching" under the category "Transceiver Options", however I don't see these parameters in Quartus. Is there somewhere else that I can enable this option to have the two different reference clock frequencies? Do I need this enabled, or is there some other way that I can switch between the two frequencies?
    >> May I know which page / section you are looking for this information ?
    >> Just trying to understand more so that we can speak apple to apple

    Or do I need to provide both clock frequencies separately? If I need to provide both clock frequencies separately, 
    >> Altera recommends you not to share TX PLL reference clock with RX transceiver reference clock for a parallel loopback design because TX PLL clock is going to be tuned to match RX recovered clock frequency.

    If I need to provide both clock frequencies separately, what pins can I use for the 148.35 MHz reference clock?
    >> it depends on the device actually , but you can refer to our design example targeted the Agilex5 devkit, that can be a good reference to map the pin
    >> Also you can refer to https://www.altera.com/design/devices/resources/pinouts#tab-blade-1-3

    Regards,

    Wincent_Altera