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Altera_Forum
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13 years ago

Wiring Optimization

Hi,

I’m now developing my custom board based on Cyclone III FPGA (EP3C120).

In my design, I have several fast input lines (3) with 10MHz base clock, 100MHz after PLL, max stages for pipeline. My Fmax is 106MHz, about 50% FPGA LE’s utilization.

Is it possible that after I’ll wire those inputs to random pins, do Pin Assignment and burn the firmware, the Fmax will drop to less then 100MHz?

What is the optimization for wiring the FPGA for thos three inputs only (the same pins side to the clock, the same Bank with the clock…)

Is there any way to know the exact pins that quartus (http://www.altera.com/products/software/quartus-ii/subscription-edition/qts-se-index.html) refer to during the compilation? (maybe if I’ll wire to the same pins I’ll have the same Fmax…)

Any help will do …:cool:

Thanks,

Idan

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The fmax can change from one compilation to another, depending on the seed you use, the operating system, the Quartus version, and any change you make to the input files. If you need a guaranteed Fmax for your system, you need to add your timing requirements for TimeQuest in a .sdc script.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you!

    But how could i do that? Knowing the "Quartus II TimeQuest Timing Analyzer Cookbook" will give me the tools i need in order to guaranteed the fmax? Is there another/other doc that i need? (note: that this code is driving after PLL from rhe upper arch)
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes, you specify your clock input frequency/ies in an SDC file, and Quartus will tell you if it can meet your requirements. If it isn't able to do it, then you can see what settings you can change to optimize timing (the timing advisor in Tools > Advisors can help you with that), or you may need to change your code to make your design pass the timing requirements.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Well your target frequency iss 100 Mhz and you are achieving 106.

    I can say you are somewhat near the border.

    As Daixiwen said the best way is to give proper constraints through SDC file, And if the Pin assignments are to be done then i think you should better do it and go for it as in future you will be doing it and you can get results soon and do some analysis.

    As per what i think suppose you fail timing after this it wont be by too much , atleast i expect that you will still be in 90 to 100 Mhz range.

    If it happens go for Seed sweep and timing switches , you can easily gain 10 MHz from that.

    Good luck :)
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    And yes forgot to answer your last qustion.

    You can refer to the fit report for the pin assignments.

    The heading will be as "Input pins" & "Output pins" and it will give you the exact pin location where the quartus placed.

    After knowing that you can give location assignments through .qsf giving the pin locations.