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Altera_Forum
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13 years ago

Wiring Optimization

Hi, I’m now developing my custom board based on Cyclone III FPGA (EP3C120). In my design, I have several fast input lines (3) with 10MHz base clock, 100MHz after PLL, max stages for pipeline. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Well your target frequency iss 100 Mhz and you are achieving 106.

I can say you are somewhat near the border.

As Daixiwen said the best way is to give proper constraints through SDC file, And if the Pin assignments are to be done then i think you should better do it and go for it as in future you will be doing it and you can get results soon and do some analysis.

As per what i think suppose you fail timing after this it wont be by too much , atleast i expect that you will still be in 90 to 100 Mhz range.

If it happens go for Seed sweep and timing switches , you can easily gain 10 MHz from that.

Good luck :)