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Altera_Forum
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14 years ago

Wiring Optimization

Hi, I’m now developing my custom board based on Cyclone III FPGA (EP3C120). In my design, I have several fast input lines (3) with 10MHz base clock, 100MHz after PLL, max stages for pipeline. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you!

But how could i do that? Knowing the "Quartus II TimeQuest Timing Analyzer Cookbook" will give me the tools i need in order to guaranteed the fmax? Is there another/other doc that i need? (note: that this code is driving after PLL from rhe upper arch)