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Altera_Forum
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14 years ago

Wiring Optimization

Hi, I’m now developing my custom board based on Cyclone III FPGA (EP3C120). In my design, I have several fast input lines (3) with 10MHz base clock, 100MHz after PLL, max stages for pipeline. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

And yes forgot to answer your last qustion.

You can refer to the fit report for the pin assignments.

The heading will be as "Input pins" & "Output pins" and it will give you the exact pin location where the quartus placed.

After knowing that you can give location assignments through .qsf giving the pin locations.