Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorWiring Optimization
Hi, I’m now developing my custom board based on Cyclone III FPGA (EP3C120). In my design, I have several fast input lines (3) with 10MHz base clock, 100MHz after PLL, max stages for pipeline. ...
Altera_ForumHonored Contributor
Honored ContributorThe fmax can change from one compilation to another, depending on the seed you use, the operating system, the Quartus version, and any change you make to the input files. If you need a guaranteed Fmax for your system, you need to add your timing requirements for TimeQuest in a .sdc script.
