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Altera_Forum
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13 years ago

Wiring Optimization

Hi, I’m now developing my custom board based on Cyclone III FPGA (EP3C120). In my design, I have several fast input lines (3) with 10MHz base clock, 100MHz after PLL, max stages for pipeline. ...
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Altera_Forum
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13 years ago

The fmax can change from one compilation to another, depending on the seed you use, the operating system, the Quartus version, and any change you make to the input files. If you need a guaranteed Fmax for your system, you need to add your timing requirements for TimeQuest in a .sdc script.