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Honored Contributor
Honored ContributorWiring Optimization
Hi, I’m now developing my custom board based on Cyclone III FPGA (EP3C120). In my design, I have several fast input lines (3) with 10MHz base clock, 100MHz after PLL, max stages for pipeline. ...
Altera_ForumHonored Contributor
Honored ContributorYes, you specify your clock input frequency/ies in an SDC file, and Quartus will tell you if it can meet your requirements. If it isn't able to do it, then you can see what settings you can change to optimize timing (the timing advisor in Tools > Advisors can help you with that), or you may need to change your code to make your design pass the timing requirements.
