what buffer element to achieve delayed output...not LCELL usage

The equivalent of what you did for Xilinx is to use LCELL.

It's not a recomended practice because the exact delay will depend on many factors: process, temperature, voltage and routing.

Try to use timing constrains instead.

Use set_output_delay -min and set_output_delay -max.

Or use set_min_delay and set_max_delay if no clock is involved.

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Try to use timing constrains instead.

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Although it can remove the routing uncertainty, PVT variation will remain.

In addition, timing constraints only utilize delays, that can be implemented with regular routing opions.

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Although it can remove the routing uncertainty, PVT variation will remain.

In addition, timing constraints only utilize delays, that can be implemented with regular routing opions.

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But, we must use LCELLs, in some cases such as implementing serveral levels delay lines.

My question is that what's one Lcell's delay time value when given a device? Or could you tell me how and where to find this value? And what the curve diagarm relationship between this delay value and PVT variations?

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Hi,

I need a delayed outputs

I don't want to use LCELL as suggested by Forum members as it is bad practice.

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Perhaps you should first explain why you think you need a delayed output since, in many cases, that's not a good practice either regardless of the implementation.

Kevin Jennings

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You can evaluate the expectable logic cell delays in timing analysis. 0.3 to 0.4 ns per logic cell is a rough estimation for Cyclone FPGAs.

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Thanks for you reply!