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Altera_Forum's avatar
Altera_Forum
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14 years ago

what buffer element to achieve delayed output...not LCELL usage

Hi, I need a delayed outputs I don't want to use LCELL as suggested by Forum members as it is bad practice. Below is a code which i used in Xilinx for same operation. Eg : (* LOCK_P...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You can evaluate the expectable logic cell delays in timing analysis. 0.3 to 0.4 ns per logic cell is a rough estimation for Cyclone FPGAs.