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Altera_Forum
Honored Contributor
Honored Contributorwhat buffer element to achieve delayed output...not LCELL usage
Hi, I need a delayed outputs I don't want to use LCELL as suggested by Forum members as it is bad practice. Below is a code which i used in Xilinx for same operation. Eg : (* LOCK_P...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Try to use timing constrains instead. --- Quote End --- Although it can remove the routing uncertainty, PVT variation will remain. In addition, timing constraints only utilize delays, that can be implemented with regular routing opions.
