Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorwhat buffer element to achieve delayed output...not LCELL usage
Hi, I need a delayed outputs I don't want to use LCELL as suggested by Forum members as it is bad practice. Below is a code which i used in Xilinx for same operation. Eg : (* LOCK_P...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Although it can remove the routing uncertainty, PVT variation will remain. In addition, timing constraints only utilize delays, that can be implemented with regular routing opions. --- Quote End --- But, we must use LCELLs, in some cases such as implementing serveral levels delay lines. My question is that what's one Lcell's delay time value when given a device? Or could you tell me how and where to find this value? And what the curve diagarm relationship between this delay value and PVT variations?
