Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Warning: Latch has unsafe behavior

I keep getting this warning when compiling my design in Quartus. I first get a warning that says 


"Verilog HDL Always Construct warning at (line# ): inferring latch(es) for variable (my variable name) which holds its previous value in one or more paths through the always construct"

then I get the message about unsafe behavior.

Expanding the warning message tells me 


"Ports D and ENA on the latch are fed by the same signal..."

I have tried many things to get it to like my code but no success. What am I missing here? Do I need to create a state machine or something?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    No, you don't need to create a state machine, you need to get rid of your latches. Quartus is telling you the names of the variables or signals in question, you need to find those in your design and get rid of them by making sure that those variables and signals always get an assignment independent of any other conditinal logic.

    Typically this is done by setting the offending variable/signal to some default value right at the begining of the process. Some examples:

    - my_sig<= '0';

    - my_sig<= last_value_of_my_sig;

    The better approach is to ditch your use of unclocked processes and simply use clocked processes and simple concurrent statements...but that suggestion, although superior typically can ignite loud disagreement on the merits of one process versus two process coding style. In any case, you need to get rid of the latches.

    Kevin Jennings
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks K_J for the hint. Its still somewhat mysterious to me since I'm a beginner, but your info along with a related post that was referenced at the bottom of this thread is starting to clear up the fog a little.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Somewhat off topic here, but can anyone suggest a good source for learning Verilog for FPGA synthesis? I have searched quite a bit and have found some snippets of good info, but a good book is hard to come by. The ones that look like they might be most useful are very expensive and I don't want to waste my money on something that is off target.

    Just to describe where I'm at, I'm a 3 decade veteran hardware designer and software programmer (mastered a number of languages in my career). Now getting into CPLD/FPGA design and I've gone through the Quartus self training materials and the Verilog and SystemVerilog tutorials. I have successfully implemented my first board with a CPLD. But it was somewhat limited. Now I want to expand the design and have gone to an FPGA because I needed a lot more logic elements. The code is a much bigger project. I am modularizing it using good software design techniques. But I am a little frustrated with the mysteries of Verilog and I need a good book on the topic of "Unlocking the Mysteries of Verilog Synthesis".

    Thanks for any pointers.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Well for verilog i can suggest Verilog HDL synthesis- A practical Primer by J.Bhaskar

    For System verilog i will strongly recommend System verilog for design by Stuart Sutherland