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Altera_Forum
Honored Contributor
Honored ContributorWarning: Latch has unsafe behavior
I keep getting this warning when compiling my design in Quartus. I first get a warning that says
"Verilog HDL Always Construct warning at (line# ): inferring latch(es) for variable (my variable...
Altera_ForumHonored Contributor
Honored ContributorWell for verilog i can suggest Verilog HDL synthesis- A practical Primer by J.Bhaskar
For System verilog i will strongly recommend System verilog for design by Stuart Sutherland
