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Altera_Forum's avatar
Altera_Forum
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13 years ago

Warning: Latch has unsafe behavior

I keep getting this warning when compiling my design in Quartus. I first get a warning that says "Verilog HDL Always Construct warning at (line# ): inferring latch(es) for variable (my variable...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Well for verilog i can suggest Verilog HDL synthesis- A practical Primer by J.Bhaskar

For System verilog i will strongly recommend System verilog for design by Stuart Sutherland