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Altera_Forum
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14 years ago

Warning: Latch has unsafe behavior

I keep getting this warning when compiling my design in Quartus. I first get a warning that says "Verilog HDL Always Construct warning at (line# ): inferring latch(es) for variable (my variable...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks K_J for the hint. Its still somewhat mysterious to me since I'm a beginner, but your info along with a related post that was referenced at the bottom of this thread is starting to clear up the fog a little.