Warning: Latch has unsafe behavior

Somewhat off topic here, but can anyone suggest a good source for learning Verilog for FPGA synthesis? I have searched quite a bit and have found some snippets of good info, but a good book is hard to come by. The ones that look like they might be most useful are very expensive and I don't want to waste my money on something that is off target.

Just to describe where I'm at, I'm a 3 decade veteran hardware designer and software programmer (mastered a number of languages in my career). Now getting into CPLD/FPGA design and I've gone through the Quartus self training materials and the Verilog and SystemVerilog tutorials. I have successfully implemented my first board with a CPLD. But it was somewhat limited. Now I want to expand the design and have gone to an FPGA because I needed a lot more logic elements. The code is a much bigger project. I am modularizing it using good software design techniques. But I am a little frustrated with the mysteries of Verilog and I need a good book on the topic of "Unlocking the Mysteries of Verilog Synthesis".

Thanks for any pointers.