Forum Discussion
Altera_Forum
Honored Contributor
13 years agoNo, you don't need to create a state machine, you need to get rid of your latches. Quartus is telling you the names of the variables or signals in question, you need to find those in your design and get rid of them by making sure that those variables and signals always get an assignment independent of any other conditinal logic.
Typically this is done by setting the offending variable/signal to some default value right at the begining of the process. Some examples: - my_sig<= '0'; - my_sig<= last_value_of_my_sig; The better approach is to ditch your use of unclocked processes and simply use clocked processes and simple concurrent statements...but that suggestion, although superior typically can ignite loud disagreement on the merits of one process versus two process coding style. In any case, you need to get rid of the latches. Kevin Jennings