VHDL newbie : configuration file does not compile

Hi,

In your configExampleConfig.vhd, use work.all

your configExample_Pkg doesn't declare counter4bits.

Be careful with

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

First, They are NOT all IEEE standards (,

Second, 'Unsigned' is always defined in STD_LOGIC_ARITH

Third, I use

LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
USE ieee.numeric_std.all;

Look at http://www.alteraforum.com/forum/showpost.php?p=112092&postcount=10

May it help you.

Dear mmTsuchi,

Many thanks for your answer.

However, it still does'nt compile, I get this message :

Info: Found 2 design units, including 1 entities, in source file src/counter4bits.vhd
    Info: Found design unit 1: counter4Bits-behavioural
    Info: Found entity 1: counter4Bits
Info: Found 2 design units, including 1 entities, in source file src/configexample.vhd
    Info: Found design unit 1: configExample-configExampleArchi
    Info: Found entity 1: configExample
Info: Found 2 design units, including 1 entities, in source file src/genericcounter.vhd
    Info: Found design unit 1: genericCounter-behavioural
    Info: Found entity 1: genericCounter
Info: Found 1 design units, including 0 entities, in source file src/configexampleconfig.vhd
    Info: Found design unit 1: configExample_conf
Info: Found 2 design units, including 0 entities, in source file src/configexample_pkg.vhd
    Info: Found design unit 1: configExample_Pkg
    Info: Found design unit 2: configExample_Pkg-body
Error (10467): VHDL Component Configuration or Component Instantiation Statement error at configExampleConfig.vhd(30): component "counter4Bits" is used but not declared

May I ask you some hints anew (attached sources with modification you suggested) ?

Cheers !

Sylvain

Hi, look at http://amouf.chez.com/syntaxe.htm#component

I don't know COMPONENT and CONFIGURATION in VHDL. I couldn't help you but I will look at this thread later. It is surely interesting !

i have spent 7 years in writing vhdl without using component and configuration (except some altera's components).

Configurations are rarely used in VHDL. There is no need to use them when you have a single architecture for an entity. And even when you have multiple architectures, there are ways you can select which one to use without having to resort to configurations.

eg. using direct instantiation

my_inst : entity my_lib.some_entity(synth_arch)
generic map (
  ...
)
port map (
  ...
);

With direct instantiation, its also possible to completly avoid component declarations as well.

Is there any reason you are using components?

--- Quote Start ---

Configurations are rarely used in VHDL.

--- Quote End ---

Nevertheless they are supported by Quartus. I've used them with an existing design. I guess, there's a syntax error in the above component configuration declaration, but I'm not aware of the syntax details. Also a limitation of the Quartus configuration feature may exist. Diy you try to compile the code with a different tool, e.g. Modelsim?

Hi FvM !

Modelsim raises the same error report !

Cheers !

Sylvain

Hi Tricky !

I think it's a good way to centralize both the design description and the architecture choices for each component used in a single file.

Then, a new programmer participating to the project after its beginning can refer to this file to get an accurate view of the whole system.

Cheers !

Sylvain

Hi mmTsuchi !

I went through http://amouf.chez.com/syntaxe.htm#component but I still don't detect any mistake in my code...

Cheers !

Sylvain