Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

VHDL newbie : configuration file does not compile

Hi ! I wrote a VHDL snippet to test "configuration" VHDL clause (see attached project). The top level design is configExample.vhd. I've got this error : Error (10467): VHDL Component C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Configurations are rarely used in VHDL. There is no need to use them when you have a single architecture for an entity. And even when you have multiple architectures, there are ways you can select which one to use without having to resort to configurations.

eg. using direct instantiation 


my_inst : entity my_lib.some_entity(synth_arch)
generic map (
  ...
)
port map (
  ...
);

With direct instantiation, its also possible to completly avoid component declarations as well.

Is there any reason you are using components?