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Altera_Forum
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Honored Contributorusing lvds
G´day !!
I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This serial data (data rate for each serial stream is 700Mbps maximum) is read with Cyclon III. What´s the best way to do this ? I found the ALTLVDS Megafunction, but i think this block has no sense, cause of the serialization factor of 1 for each channel used in my system. But what´s the best way to read and process the sampled input data ?? Is it possible to wire this LVDS Serial data direct to a PIO ??? hope someone can help me greets !!!45 Replies
Altera_Forum--- Quote Start --- The serialisation factor in your system is actually 14. The ALTLVDS does not support this, but you could set it to handle a deserialisation of 7 bits and concatenate two 7-bit packets into one 14 bit. ALTLVDS however uses a PLL to sample the inputs, so if you have multiple devices, ADCs in this case) you may run out of PLLs. However as the outputs of the ADC are nicely source synchronous and are accompanied by a dataclock and a frame-indicator , you can easily deserialise the ADC data channels with simple shiftregisters. Feed the inputs into a DDR-In block and then serialise the 2 bits in a 7-bit shiftregister each. assemble the 2 7-bit buses into a 14-bit bus and define the right moment to register it. You need to do some work to constrain all this though. I have done this for ADS527x and AD9222 octal ADCs, unfortunately my code is in AHDL (I do use VHDL nowadays). --- Quote End --- Hi Josy, If i run out of PLLs, how to connect the rest DCO signals? Can i connect them to normal LVDS pairs?- Altera_Forum--- Quote Start --- Jerry, I haven't used altlvds, way too complicated for me :) I assumed you were writing your own deserialiser. Regards, Josy --- Quote End --- Hi Josy, I remember that you used AD9222 deivces. How about the ADC's dirving circuit design? I'm thinking about these circuit. Our previous design used AD9218, and AD8138 as ADC's driver. However, for multi-channels LVDS output ADCs, ADI doesn't recommend using amplifiers as driver. The reason is that:"the noise of performance of most amplifiers is not adequate to achieve the true performance of the AD9222/AD9633/AD9681." Our application is of dc-coupled, so amplifiers are very suited for our app. Do you think the transformer coupled configuration is belone of DC-coupled desgin?
- Altera_Forum
Jerry,
I haven't used altlvds, way too complicated for me :) I assumed you were writing your own deserialiser. Regards, Josy - Altera_Forum--- Quote Start --- You don't need a bitslip module, as you can derive a signal from the FR-signal to clock the final two 14 bit words into to the original base-clock domain. Regards, Josy --- Quote End --- Hi Josy, I know, currently i'm testing one ADC chip implemented by using altlvds module. If the parallel lvds output data doesn't align with word boundary, the core logic should generate one pulse to feed rx_data_align port. Untill the output data align with word boundary. Here, is the word boundary also can be indicated by FR-signal?
- Altera_Forum--- Quote Start --- I'm testing LVDS module in Quartus II, can you tell me about implementing bitslip method? --- Quote End --- You don't need a bitslip module, as you can derive a signal from the FR-signal to clock the final two 14 bit words into to the original base-clock domain. Regards, Josy
- Altera_Forum--- Quote Start --- The picture on page 8 in the data-sheet of the LTM9010 shows 2 ADC words are transmitted per FR-cycle (using 7 DCO clocks) You can use an internal clock for the DDR-IN and the following shift-registers, but then you will have to align the incoming LVDS data using extra logic. It would save you from routing the 6 * 2 (*2) wires for the DCO and the FR signals. If you have enough clock inputs available on your Stratix device, I would recommend using DCO and FR; it gives you a nice static timing closure. Synchronisation between devices: the only concern is that the encoding clock is synchronous for all ADC-chips: keeping them equal in length is one thing. The other is perhaps drive them from a clock distribution IC giving you very tight timing, it depends on your requirements. Regards, Josy --- Quote End --- Hello Josy, Thanks for you help. I'm testing LVDS module in Quartus II, can you tell me about implementing bitslip method?
- Altera_Forum--- Quote Start --- Is here should be 7-bit? Do you have some thought about the synchronization among channels and devices? Can i use internal system clock as the shift-regiters clock? And the ADCs' DCO signals can't be routed to FPGA? --- Quote End --- The picture on page 8 in the data-sheet of the LTM9010 shows 2 ADC words are transmitted per FR-cycle (using 7 DCO clocks) You can use an internal clock for the DDR-IN and the following shift-registers, but then you will have to align the incoming LVDS data using extra logic. It would save you from routing the 6 * 2 (*2) wires for the DCO and the FR signals. If you have enough clock inputs available on your Stratix device, I would recommend using DCO and FR; it gives you a nice static timing closure. Synchronisation between devices: the only concern is that the encoding clock is synchronous for all ADC-chips: keeping them equal in length is one thing. The other is perhaps drive them from a clock distribution IC giving you very tight timing, it depends on your requirements. Regards, Josy
- Altera_Forum
Hi josyb,
Thanks for you reply. --- Quote Start --- delivering two 14-bit samples every other base clock, --- Quote End --- Is here should be 7-bit? Do you have some thought about the synchronization among channels and devices? Can i use internal system clock as the shift-regiters clock? And the ADCs' DCO signals can't be routed to FPGA? - Altera_Forum
Jerry,
800Mbps will result in a 400 MHz clock,which is delivered by the ADC, usually 90 degree shifted (center-aligned). But this clock will only be used to shift the first 4 (5, 6, 7 or 8 ) stages resulting into two 4 (5,6,7 or 8) vectors that will then be combined to the final 8 (10,12,14 or 16) bit word. The ADC usually has a frameclock signal that you can derive a signal from to transfer the received word back into the base clock of 100 MHz which can be handled 'hands down' by the FPGA fabric The LTM9010 in 14-bit 2-Lane mode is only slightly more complicated in that it sends out a half-rate FR-clock, delivering two 14-bit samples every other base clock, but you can multiplex that back up to one 14-bit sample per clock. Regards, Josy - Altera_Forum--- Quote Start --- The Device Datasheet doesn't mention any difference between Row and Column IO, so I'm pretty sure that 700 Mbps will be fine. But you can easily try that out ... --- Quote End --- Hi josyb, ADC's output speed is up to 1.6Gbps, even run at 2-lane mode, the LVDS pairs speed at FPGA side will be 800Mbps. If LVDS pairs connect to column I/O LVDS pairs, means shift register will run at 800MHz. Does core logic run at so high speed?
