using lvds

Jerry,

800Mbps will result in a 400 MHz clock,which is delivered by the ADC, usually 90 degree shifted (center-aligned). But this clock will only be used to shift the first 4 (5, 6, 7 or 8 ) stages resulting into two 4 (5,6,7 or 8) vectors that will then be combined to the final 8 (10,12,14 or 16) bit word. The ADC usually has a frameclock signal that you can derive a signal from to transfer the received word back into the base clock of 100 MHz which can be handled 'hands down' by the FPGA fabric

The LTM9010 in 14-bit 2-Lane mode is only slightly more complicated in that it sends out a half-rate FR-clock, delivering two 14-bit samples every other base clock, but you can multiplex that back up to one 14-bit sample per clock.

Regards,

Josy