Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

using lvds

G´day !! I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This seri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

--- Quote Start ---

You don't need a bitslip module, as you can derive a signal from the FR-signal to clock the final two 14 bit words into to the original base-clock domain.

Regards,

Josy

--- Quote End ---

Hi Josy,

I know, currently i'm testing one ADC chip implemented by using altlvds module. If the parallel lvds output data doesn't align with word boundary, the core logic should generate one pulse to feed rx_data_align port. Untill the output data align with word boundary. Here, is the word boundary also can be indicated by FR-signal?