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Honored Contributor
Honored Contributorusing lvds
G´day !! I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This seri...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The Device Datasheet doesn't mention any difference between Row and Column IO, so I'm pretty sure that 700 Mbps will be fine. But you can easily try that out ... --- Quote End --- Hi josyb, ADC's output speed is up to 1.6Gbps, even run at 2-lane mode, the LVDS pairs speed at FPGA side will be 800Mbps. If LVDS pairs connect to column I/O LVDS pairs, means shift register will run at 800MHz. Does core logic run at so high speed?
