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Altera_Forum
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15 years ago

using lvds

G´day !! I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This seri...
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Altera_Forum
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10 years ago

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The picture on page 8 in the data-sheet of the LTM9010 shows 2 ADC words are transmitted per FR-cycle (using 7 DCO clocks)

You can use an internal clock for the DDR-IN and the following shift-registers, but then you will have to align the incoming LVDS data using extra logic. It would save you from routing the 6 * 2 (*2) wires for the DCO and the FR signals. If you have enough clock inputs available on your Stratix device, I would recommend using DCO and FR; it gives you a nice static timing closure.

Synchronisation between devices: the only concern is that the encoding clock is synchronous for all ADC-chips: keeping them equal in length is one thing. The other is perhaps drive them from a clock distribution IC giving you very tight timing, it depends on your requirements.

Regards,

Josy

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Hello Josy,

Thanks for you help.

I'm testing LVDS module in Quartus II, can you tell me about implementing bitslip method?