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Altera_Forum
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Honored Contributorusing lvds
G´day !!
I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This serial data (data rate for each serial stream is 700Mbps maximum) is read with Cyclon III. What´s the best way to do this ? I found the ALTLVDS Megafunction, but i think this block has no sense, cause of the serialization factor of 1 for each channel used in my system. But what´s the best way to read and process the sampled input data ?? Is it possible to wire this LVDS Serial data direct to a PIO ??? hope someone can help me greets !!!45 Replies
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- Altera_Forum
Hi josyb,
Is it means that 350MHz would get 700Mbps data rate? Cause of DDR. - Altera_Forum--- Quote Start --- Hi josyb, Is it means that 350MHz would get 700Mbps data rate? Cause of DDR. --- Quote End --- Yes, it will.
- Altera_Forum--- Quote Start --- Yes, it will. --- Quote End --- Hi josyb, Thanks for you reply! I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output. I don't know the maximum speed of these column I/O LVDS pairs, and the datasheet only give the row I/O LVDS pairs speed range. Do you think the column I/O lvds pairs can run at 700Mbps or more than this speed?
- Altera_Forum--- Quote Start --- I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output. I don't know the maximum speed of these column I/O LVDS pairs, and the datasheet only give the row I/O LVDS pairs speed range. Do you think the column I/O lvds pairs can run at 700Mbps or more than this speed? --- Quote End --- The Device Datasheet doesn't mention any difference between Row and Column IO, so I'm pretty sure that 700 Mbps will be fine. But you can easily try that out ...
- Altera_Forum--- Quote Start --- The Device Datasheet doesn't mention any difference between Row and Column IO, so I'm pretty sure that 700 Mbps will be fine. But you can easily try that out ... --- Quote End --- Hi josyb, ADC's output speed is up to 1.6Gbps, even run at 2-lane mode, the LVDS pairs speed at FPGA side will be 800Mbps. If LVDS pairs connect to column I/O LVDS pairs, means shift register will run at 800MHz. Does core logic run at so high speed?
- Altera_Forum
Jerry,
800Mbps will result in a 400 MHz clock,which is delivered by the ADC, usually 90 degree shifted (center-aligned). But this clock will only be used to shift the first 4 (5, 6, 7 or 8 ) stages resulting into two 4 (5,6,7 or 8) vectors that will then be combined to the final 8 (10,12,14 or 16) bit word. The ADC usually has a frameclock signal that you can derive a signal from to transfer the received word back into the base clock of 100 MHz which can be handled 'hands down' by the FPGA fabric The LTM9010 in 14-bit 2-Lane mode is only slightly more complicated in that it sends out a half-rate FR-clock, delivering two 14-bit samples every other base clock, but you can multiplex that back up to one 14-bit sample per clock. Regards, Josy - Altera_Forum
Hi josyb,
Thanks for you reply. --- Quote Start --- delivering two 14-bit samples every other base clock, --- Quote End --- Is here should be 7-bit? Do you have some thought about the synchronization among channels and devices? Can i use internal system clock as the shift-regiters clock? And the ADCs' DCO signals can't be routed to FPGA? - Altera_Forum--- Quote Start --- Is here should be 7-bit? Do you have some thought about the synchronization among channels and devices? Can i use internal system clock as the shift-regiters clock? And the ADCs' DCO signals can't be routed to FPGA? --- Quote End --- The picture on page 8 in the data-sheet of the LTM9010 shows 2 ADC words are transmitted per FR-cycle (using 7 DCO clocks) You can use an internal clock for the DDR-IN and the following shift-registers, but then you will have to align the incoming LVDS data using extra logic. It would save you from routing the 6 * 2 (*2) wires for the DCO and the FR signals. If you have enough clock inputs available on your Stratix device, I would recommend using DCO and FR; it gives you a nice static timing closure. Synchronisation between devices: the only concern is that the encoding clock is synchronous for all ADC-chips: keeping them equal in length is one thing. The other is perhaps drive them from a clock distribution IC giving you very tight timing, it depends on your requirements. Regards, Josy
- Altera_Forum--- Quote Start --- The picture on page 8 in the data-sheet of the LTM9010 shows 2 ADC words are transmitted per FR-cycle (using 7 DCO clocks) You can use an internal clock for the DDR-IN and the following shift-registers, but then you will have to align the incoming LVDS data using extra logic. It would save you from routing the 6 * 2 (*2) wires for the DCO and the FR signals. If you have enough clock inputs available on your Stratix device, I would recommend using DCO and FR; it gives you a nice static timing closure. Synchronisation between devices: the only concern is that the encoding clock is synchronous for all ADC-chips: keeping them equal in length is one thing. The other is perhaps drive them from a clock distribution IC giving you very tight timing, it depends on your requirements. Regards, Josy --- Quote End --- Hello Josy, Thanks for you help. I'm testing LVDS module in Quartus II, can you tell me about implementing bitslip method?
