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Fdominguez's avatar
Fdominguez
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2 years ago

TRACE Interface through FPGA on Intel's Agilex 7 device not outputting clock

Hi.

I am trying to validate a TRACE interface coming from Agilex’s HPS through the FPGA IO to a Mictor connector, but I am having issues getting the TRACECLK to show up. Currently I have a DSTREAM-PT interface working and can see the TRACE DATA signals toggling but not the clock.

I added to the HPS Core the 16-bit width TRACE interface through Quartus, and made the Coresight Trace clock 50MHz as it’s the slowest to make sure we could see a clock. After synthesis I see the trace_s2f_clk output is actually connected from the S2F module as TPIU_TRACE_CLK to the IO pins but once we run a test through the ARM-DS I don’t see a clock coming out of the pin, but I do see data toggling through a scope

I also made sure that looking at this register all clocks were enabled

https://www.intel.com/content/www/us/en/programmable/hps/agilex7/hps.html#topic/cvf1561687518174.html

I find there is a lack of documentation about this feature and haven’t been able to find the reason of it not working. Am I missing something that I should be enabling either through Quartus or through a SW register? Any suggestions to look at?

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14 Replies

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Fdominguez,


    I am still consulting the team regarding the matter. May I know if the previous provided document link does help to answer your question.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Fdominguez,


    May I know if you can see the trace data but you are not able to identify the data bit without the clock?


    Thanks.

    Regards,

    Aik Eu


    • Fdominguez's avatar
      Fdominguez
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi Aik

      To answer all your questions:

      1. I have referenced to the TRM and haven't really found much information about enabling/disabling the TRACE clock. I know the FPGA generates a connection to the Trace Port Interface Unit (TPIU) and that I have tried with cs_atclk clocks ranging from 50 to 200MHz configured through Quartus

      2. We have hooked up an oscilloscope to the TRACE data lanes and can see that there is toggling when testing with the DSTREAM, but we can process the data as we are missing the clock signal which we can't see on the oscilloscope nor is detected by the DSTREAM

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Fdominguez,


    I get the information from the team where you can try to troubleshoot by checking/probing on the HPS IO instead as the path to the trace clock and data is sharing the same path to the FPGA output routing.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Fdominguez,


    Do let me know if there is any further follow up on the case.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Fdominguez,


    May I know is there any further update on the matter?


    Thanks.

    Regards,

    Aik Eu


    • Fdominguez's avatar
      Fdominguez
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi Aik,

      Sorry the delay replying I was having issues login into my Intel account.

      I didn't see your latest update to test the Clock only through the HPS I/O. I am not certain we can do that as as far as I remember we dont have available I/O but I will double check on that.

      From the image you sent you are suggesting I should use an FPGA Clock source to power the TRACE interface? I see I can potentially do that but on quartus 23.1 I can only do it on auto-place mode and that would change all my HPS IO which I have used the advanced feature for more personalized placement. Are you suggesting for me to try that?

      Best,

      Ferencz

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Fdominguez,


    May I know the board being used is a custom Agilex 7 board?

    From your question, remain using the clock from HPS clock manager but not using the FPGA clock source.

    The only thing which engineering suggest is to check is the clock routing to the HPS IO instead of the FPGA IO as the path is more direct from the clock source.


    Thanks.

    Regards,

    Aik Eu