Forum Discussion
aikeu
Regular Contributor
2 years agoHi Fdominguez,
May I know the board being used is a custom Agilex 7 board?
From your question, remain using the clock from HPS clock manager but not using the FPGA clock source.
The only thing which engineering suggest is to check is the clock routing to the HPS IO instead of the FPGA IO as the path is more direct from the clock source.
Thanks.
Regards,
Aik Eu