Forum Discussion
aikeu
Regular Contributor
2 years agoHi Fdominguez,
May I know if you can see the trace data but you are not able to identify the data bit without the clock?
Thanks.
Regards,
Aik Eu
- Fdominguez2 years ago
New Contributor
Hi Aik
To answer all your questions:
1. I have referenced to the TRM and haven't really found much information about enabling/disabling the TRACE clock. I know the FPGA generates a connection to the Trace Port Interface Unit (TPIU) and that I have tried with cs_atclk clocks ranging from 50 to 200MHz configured through Quartus
2. We have hooked up an oscilloscope to the TRACE data lanes and can see that there is toggling when testing with the DSTREAM, but we can process the data as we are missing the clock signal which we can't see on the oscilloscope nor is detected by the DSTREAM