To build a FIFO using SRAM

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I would like to build a DCFIFO using a SRAM chip on DE2-115. Any idea on where i should start?

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You'd be designing a FIFO, not a (dual-clock) DCFIFO.

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I know SRAM reads and writes on a different clock cycle as the dataIn and dataOut share the same bidirectional databus, but do you think i can increase the frequency by 2 times (based on spec sheet, max performance of my SRAM is 125MHz), meaning if my ADC data coming in at 60MHz, i am inputting data and outputting data to/from my SRAM on an alternate cycle at 120MHz. is it possible? if yes, what are the things i need to be concerned about?

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You'd likely want to perform burst writes and reads to the SRAM (its likely a clock or two faster, since there is no need for the SRAM controller FSM to conservatively insert bus turn-around cycles).

So you'd have your ADC write to a DCFIFO or dual-ported RAM internal to the FPGA at 60MHz, and then once the FIFO was filled above a threshold, start a DMA to the SRAM at its maximum speed. Then when that DMA is done, perform another DMA to read older data back.

However, what's the point? You're just adding delay. Of course, if you are aligning multiple different data streams, this might be what you want.

Cheers,

Dave

Dave,

Is there any DMA IP core in Quartus 2 i could use? or do i need DMA if i am writing to a SRAM? what does DMA do? can i just use a controller(with a up counter for address bus, etc..) ?

regards,

Michael

Hi Michael,

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Is there any DMA IP core in Quartus 2 i could use? or do i need DMA if i am writing to a SRAM? what does DMA do? can i just use a controller(with a up counter for address bus, etc..) ?

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Read the Altera documentation on SOPC Builder (old tool) and Qsys (newer tool), and the Avalon bus specification.

What you want is an SOPC/Qsys system with an Avalon-ST ADC source, an SGDMA controller, an SRAM controller, and an Avalon-MM master (eg. the JTAG-to-Avalon-MM bridge or a NIOS II processor).

You will need to design the ADC to Avalon-ST streaming component (its pretty simple though). You can then use the SGDMA controller for Avalon-ST (ADC) to Avalon-MM (SRAM) data movement.

What are you trying to do with the data? Capture snapshots of data, or continuously stream it somewhere (other than the SRAM)?

Cheers,

Dave

My ADC is sampling at 65MHz. i am trying to capture 2MB(1024000 samples) of ADC data and send to through QuickUSB at 30MB/s, and graph it on my laptop continuously .

Do you think NIOS 2 is capable of handling 65MHz data? or the SRAM controller is running at slower speed than 65MHz?

regards,

Michael

Hi Michael,

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My ADC is sampling at 65MHz. i am trying to capture 2MB(1024000 samples) of ADC data and send to through QuickUSB at 30MB/s, and graph it on my laptop using Matlab.

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What is the bit-width of the ADC?

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Do you think NIOS 2 is capable of handling 65MHz data? or the SRAM controller is running at slower speed than 65MHz?

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The NIOS II never actually touches the ADC data, its just there to coordinate movement of the data.

The key design parameter is whether you can find a memory target that can maintain a sustained data transfer rate of 65MHz x ADC bit-width.

You'll need to see whether the SRAM or SDRAM on the DE-115 can handle that data rate.

Cheers,

Dave

Dave,

The width of ADC is 14 bits, but i am sending 16 bits across every transfer.

The SRAM on my DE2-115 has access time of 8ns, so its maximum performance is 125MHz, so i guess it is more than enough to hold 2MB of sample from the ADC at 65 MHz. Am i right on this? I only need a "window" (1024000 ADC samples), not to stream continuous raw data, as some portion of the data will be lost(which is fine).

I want to see the streaming of "window" of data.

Regards,

Michael

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The width of ADC is 14 bits, but i am sending 16 bits across every transfer.

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Ok.

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The SRAM on my DE2-115 has access time of 8ns, so its maximum performance is 125MHz, so i guess it is more than enough to hold 2MB of sample from the ADC at 65 MHz. Am i right on this?

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Have you checked the SRAM controller timing? An SRAM write needs three clock cycles; chip select asserted with write-enable high, then write-enable low, then write-enable high again. This pulse sequence is required to meet all of the timing parameters of the SRAM. To get 65MHz writes to 16-bit SRAM, your FSM will need to run at 3 x 65MHz = 195MHz, which seems do-able, but you'll have to check.

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I only need a "window" (1024000 ADC samples), not to stream continuous raw data, as some portion of the data will be lost(which is fine).

I want to see the streaming of "window" of data.

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However, the window is consecutive samples at 65MHz, so that is the data rate you need to support while capturing the data.

Cheers,

Dave

Err.. isn't the part on the DE2-115 a 10 ns access time part?

IS61WV102416BLL-10

Anyway, it supports back to back write operation, so he can write at 100 or 125 MHz.

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Err.. isn't the part on the DE2-115 a 10 ns access time part?

IS61WV102416BLL-10

Anyway, it supports back to back write operation, so he can write at 100 or 125 MHz.

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If your FPGA has a clock-to-output uncertainty of 0ns, then sure you would get a 10ns pulse out of a 100MHz clock. However, realistically, you will have clock to output delays on the orders of tco(min) = 2ns, tco(max)=4ns (or perhaps larger), so each write low assertion time would need to be two clocks to guarantee you meed the SRAM 10ns write-pulse low time timing.

It depends how robust he needs the design to be.

Cheers,

Dave