To build a FIFO using SRAM

Hi Michael,

--- Quote Start ---

Is there any DMA IP core in Quartus 2 i could use? or do i need DMA if i am writing to a SRAM? what does DMA do? can i just use a controller(with a up counter for address bus, etc..) ?

--- Quote End ---

Read the Altera documentation on SOPC Builder (old tool) and Qsys (newer tool), and the Avalon bus specification.

What you want is an SOPC/Qsys system with an Avalon-ST ADC source, an SGDMA controller, an SRAM controller, and an Avalon-MM master (eg. the JTAG-to-Avalon-MM bridge or a NIOS II processor).

You will need to design the ADC to Avalon-ST streaming component (its pretty simple though). You can then use the SGDMA controller for Avalon-ST (ADC) to Avalon-MM (SRAM) data movement.

What are you trying to do with the data? Capture snapshots of data, or continuously stream it somewhere (other than the SRAM)?

Cheers,

Dave