To build a FIFO using SRAM

Hi Michael,

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My ADC is sampling at 65MHz. i am trying to capture 2MB(1024000 samples) of ADC data and send to through QuickUSB at 30MB/s, and graph it on my laptop using Matlab.

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What is the bit-width of the ADC?

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Do you think NIOS 2 is capable of handling 65MHz data? or the SRAM controller is running at slower speed than 65MHz?

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The NIOS II never actually touches the ADC data, its just there to coordinate movement of the data.

The key design parameter is whether you can find a memory target that can maintain a sustained data transfer rate of 65MHz x ADC bit-width.

You'll need to see whether the SRAM or SDRAM on the DE-115 can handle that data rate.

Cheers,

Dave