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The width of ADC is 14 bits, but i am sending 16 bits across every transfer.
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Ok.
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The SRAM on my DE2-115 has access time of 8ns, so its maximum performance is 125MHz, so i guess it is more than enough to hold 2MB of sample from the ADC at 65 MHz. Am i right on this?
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Have you checked the SRAM controller timing? An SRAM write needs three clock cycles; chip select asserted with write-enable high, then write-enable low, then write-enable high again. This pulse sequence is required to meet all of the timing parameters of the SRAM. To get 65MHz writes to 16-bit SRAM, your FSM will need to run at 3 x 65MHz = 195MHz, which seems do-able, but you'll have to check.
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I only need a "window" (1024000 ADC samples), not to stream continuous raw data, as some portion of the data will be lost(which is fine).
I want to see the streaming of "window" of data.
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However, the window is consecutive samples at 65MHz, so that is the data rate you need to support while capturing the data.
Cheers,
Dave
Honored Contributor
