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Honored Contributor
Honored ContributorTo build a FIFO using SRAM
Hi, I would like to build a DCFIFO using a SRAM chip on DE2-115. Any idea on where i should start? I know SRAM reads and writes on a different clock cycle as the dataIn and dataOut share t...
Altera_ForumHonored Contributor
Honored ContributorDave,
The width of ADC is 14 bits, but i am sending 16 bits across every transfer. The SRAM on my DE2-115 has access time of 8ns, so its maximum performance is 125MHz, so i guess it is more than enough to hold 2MB of sample from the ADC at 65 MHz. Am i right on this? I only need a "window" (1024000 ADC samples), not to stream continuous raw data, as some portion of the data will be lost(which is fine). I want to see the streaming of "window" of data. Regards, Michael
