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Honored Contributor
Honored ContributorTo build a FIFO using SRAM
Hi, I would like to build a DCFIFO using a SRAM chip on DE2-115. Any idea on where i should start? I know SRAM reads and writes on a different clock cycle as the dataIn and dataOut share t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Err.. isn't the part on the DE2-115 a 10 ns access time part? IS61WV102416BLL-10 Anyway, it supports back to back write operation, so he can write at 100 or 125 MHz. --- Quote End --- If your FPGA has a clock-to-output uncertainty of 0ns, then sure you would get a 10ns pulse out of a 100MHz clock. However, realistically, you will have clock to output delays on the orders of tco(min) = 2ns, tco(max)=4ns (or perhaps larger), so each write low assertion time would need to be two clocks to guarantee you meed the SRAM 10ns write-pulse low time timing. It depends how robust he needs the design to be. Cheers, Dave
