Timing Slacks inside Altera IP

Hi,

I am compiling my design for the device 10AX115N2F40I2SG using:

Quartus Version: 22.1std.2 (Build 922, 07/20/2023, Standard Edition)

I am encountering timing violations (negative slack) on the clock a10_internal_oscillator_clock0 across all synthesis seeds. Due to these violations, I am unable to close timing on my design.

From my analysis, the failing paths appear to be internal to the Intel (Altera) IP, for example:

From:

ddr3_phy_wrapper48:ALTERA_DDR.ddr3_phy_wrapper_u|se_phy_master:u_qm2_phy|se_phy_master_altera_emif_221_zihdyxy:emif_0|se_phy_master_altera_emif_arch_nf_221_lnlpemi:arch|se_phy_master_altera_emif_arch_nf_221_lnlpemi_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|iopll_bootstrap:gen_pll_dprio.inst_iopll_bootstrap|gen_pll_dprio.r_dprio_writedata_in_use~RTM

To:

|ddr3_phy_wrapper48:ALTERA_DDR.ddr3_phy_wrapper_u|se_phy_master:u_qm2_phy|se_phy_master_altera_emif_221_zihdyxy:emif_0|se_phy_master_altera_emif_arch_nf_221_lnlpemi:arch|se_phy_master_altera_emif_arch_nf_221_lnlpemi_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~dprio_reg

My understanding is that this clock is only active during PLL calibration at device power-up and is not used during normal functional operation.

Given this, I would like to confirm whether it is safe and appropriate to constrain these paths as false paths. For example:

"set_false_path -from [get_clocks {a10_internal_oscillator_clock0}]"

Could you please advise if this approach is valid, or if there is a recommended way to properly constrain these paths?

I attached an image of the slacks.