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Omer1's avatar
Omer1
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4 months ago

Timing Slacks inside Altera IP

Hi, I am compiling my design for the device 10AX115N2F40I2SG using: Quartus Version: 22.1std.2 (Build 922, 07/20/2023, Standard Edition) I am encountering timing violations (negative slack) on the...
Core Logic
RichardT_altera's avatar
RichardT_altera
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4 months ago

Could you please provide the QAR design file (Project → Archive Project) so that I can investigate this further?
Kindly share the file with me via private message (PM).

Regards,
RIchard Tan

RichardT_altera's avatar
RichardT_altera
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4 months ago

Hi Omer1 

Could you help to share the QAR design file (Project → Archive Project) so that I can investigate this further?
Kindly share the file with me via private message (PM).

Regards,
Richard Tan
 

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    4 months ago

    Hi Omer1 

    As we have not receive any further response, we will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

    Thank you for engaging with us!

    Best regards,
    Richard Tan