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Omer1's avatar
Omer1
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4 months ago

Timing Slacks inside Altera IP

Hi, I am compiling my design for the device 10AX115N2F40I2SG using: Quartus Version: 22.1std.2 (Build 922, 07/20/2023, Standard Edition) I am encountering timing violations (negative slack) on the...
Core Logic
sstrell's avatar
sstrell
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4 months ago

Are there any warnings or issues shown for the EMIF IP since this appears to be referring to one of the IOPLLs for the EMIF in an I/O bank?  What is your refclk for the IP and what speed do you have the EMIF running at (internal and external)?

  • Omer1's avatar
    Omer1
    Icon for New Contributor rankNew Contributor
    4 months ago

    Hi sstrel,

    I don't see any warnings or issues regarding the se_phy_master.qsys (EMIF IP).

    The refclk is 266 Mhz. The EMIF running with clock of 1066.667 Mhz.

    Attached in image.

    BTW - I see that not all these slacks are related to the EMIF IP, but all are related to "iopll_bootstrap".

    For example:

    From:

    tod_sync_pll:u_tod_sync_pll|tod_sync_pll_altera_iopll_221_fsgzxmq:iopll_0|altera_iopll:altera_iopll_i|iopll_bootstrap:iopll_bootstrap_inst|gen_pll_dprio.r_dprio_addr_in_use~RTM_1

    To:

    tod_sync_pll:u_tod_sync_pll|tod_sync_pll_altera_iopll_221_fsgzxmq:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst~dprio_reg

    Attached an image.

    I think we have an issue which related to the a10_internal_oscillator_clock0 (which is an internal clock that I don't have the ability to affect) and not to the EMIF IP.