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Omer1's avatar
Omer1
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4 months ago

Timing Slacks inside Altera IP

Hi, I am compiling my design for the device 10AX115N2F40I2SG using: Quartus Version: 22.1std.2 (Build 922, 07/20/2023, Standard Edition) I am encountering timing violations (negative slack) on the...
Core Logic
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 months ago

Hi Omer1,

 

Please help to provide more information to help on clarify the issue.

 

I guess the a10_internal_oscillator_clock0 is a reference clock to EMIF IP.

Correct me if I'm wrong. 

Any other instance that used same clock for the clock source in your design?

 

Is there any other instances that has been connected to EMIF IP?

 

Can you try to remove other IP and fit the EMIF IP first in the design?

Then observe if the timing violation is still there.

 

Regards,

Adzim

Omer1's avatar
Omer1
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4 months ago

Hi Adzim,

  1. The a10_internal_oscillator_clock0 is not a reference clock to EMIF IP.

The a10_internal_oscillator_clock0 is internal clock (which is an internal clock that I don't have the ability to affect), and all our ref clocks are from PINs.

2. I have other instances that uses a10_internal_oscillator_clock0 clock, like this block:

tod_sync_pll_altera_iopll_221_fsgzxmq:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst~dprio_reg

So is looks like the issue is not related to the EMIF IP, but to a10_internal_oscillator_clock0.

I see that not all these slacks are related to the EMIF IP, but all are related to "iopll_bootstrap".

For example:

From:

tod_sync_pll:u_tod_sync_pll|tod_sync_pll_altera_iopll_221_fsgzxmq:iopll_0|altera_iopll:altera_iopll_i|iopll_bootstrap:iopll_bootstrap_inst|gen_pll_dprio.r_dprio_addr_in_use~RTM_1

To:

tod_sync_pll:u_tod_sync_pll|tod_sync_pll_altera_iopll_221_fsgzxmq:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst~dprio_reg

Attached an image.

I think we have an issue which related to the a10_internal_oscillator_clock0 (which is an internal clock that I don't have the ability to affect) and not to the EMIF IP.