Forum Discussion
Honored ContributorTiming requirements to a part of a circuit
Does anybody know how to set timing requirements to a part of a circuit? I mean there is a critical part of a circuit that needs frequency optimization, and it's not rational to apply frequency constraint to all block. Thanks in advance.
23 Replies
Altera_Forum--- Quote Start --- kaz, is it enough for a simple project just two lines for sdc file: create_clock -period 10.000 -waveform {0.000 5.000} -name fast_clk [get_ports {fast_clk}] set_max_delay -from [get_pins inst21 [*]|q] -to [get_pins inst24 [*]|d] 20 ? If I use 2 ns instead of 20 there will be no timing error. Thank you both for your support. --- Quote End --- Your path inst21 to inst24 is enabled once every two clocks so apply multicycle (if it is failing), not set max delay- Altera_Forum
Tricky, fortunatelly, my project (I mean my real project, not example from the cookbook) works normally with current clk frequency (96 MHz - fast version and just 24 MHz - slow version). However, in some cases I use such chains like reg (clk,ena)->logic->reg (clk)->logic->reg(ena,clk). Here I use reg(clk) just to divide long logic chain into two parts (I guess it facilitates routing). Multicycle analysis isn't applicable here. TA warns me and shows negative slacks for such circuits, because it takes all these regs as regs(clk). What I do is control delays in this paths by myself and make sure that slacks are OK . Of, course, as long as my project works I'll not do any tedious work :) But I would like to study how to use TA because it's a useful thing.
kaz, is it enough for a simple project just two lines for sdc file: create_clock -period 10.000 -waveform {0.000 5.000} -name fast_clk [get_ports {fast_clk}] set_max_delay -from [get_pins inst21 [*]|q] -to [get_pins inst24 [*]|d] 20 ? If I use 2 ns instead of 20 there will be no timing error. Thank you both for your support. - Altera_Forum--- Quote Start --- I'm just trying different possible approaches. That was my mistake when I used set_multicycle_path and set_max_delay at the same time. Yes, you are right, multicycle relaxes constraints. I'm thinking that in some situations we can use set max delay just to constraint one or several data paths rather then using multicycle together with clock constraint --- Quote End --- set_min_delay and set_max_delay: These constraints can emulate multicycle constraints. set_max_delay overrides SMC and set_min_delay overrides HMC. For example SMC of 2 and HMC of 1 means set_max_delay to 2 clock periods and set_min_delay to 0 clock period. However, delay values are in time units rather than clock periods and so can be defined with higher resolution.
- Altera_Forum
the main approach is just to set a clock constraint with any multi-cycle constraints you require. If there are problems, fix the RTL.
If you then decide you cannot fiddle with the RTL any more, only then should you consider using logic lock regions. Only now when you have a few failing paths should you consider max_delay constraints. Going down this road is a lond and tedious one with lots of trial and error. Much easier to stick with clock constraints. - Altera_Forum
I'm just trying different possible approaches. That was my mistake when I used set_multicycle_path and set_max_delay at the same time. Yes, you are right, multicycle relaxes constraints. I'm thinking that in some situations we can use set max delay just to constraint one or several data paths rather then using multicycle together with clock constraint
- Altera_Forum
set max delay and multicycle path constraints are usually used to do different things. Max delay will make the fitter work harder, and multicycle path makes it easier for the fitter. They are not the same thing.
I still dont understand why you are doing this - if you are meeting constraints with just a clock constraint, why are you trying to overconstrain it? do you have problems with your design? The first method to fix re-occuring problems should be to fix the RTL code (add more pipelining) as this is the quickest and easiest fix. - Altera_Forum
I didn't mean to use max delay with multicycle constraint. I just thought it's possible to restrict a bottleneck without specifing clk frequency and multicycle constraint. So, will it work without set_multicycling_path commands?
- Altera_Forum
max delay applies an absolute timing relationship, in nanoseconds between two nodes. It is NOT related to the clocks. If these are 2 registers and you already have clock constraints, then this max delay constraint is already infered at the clock delay. putting a max delay constraint of 2ns is like having a clock constraint of 500Mhz, so you are probably over-constraining the design.
This is NOT how you apply multicycle constraints. - Altera_Forum
set_max_delay -from [get_pins inst21[*]|q] -to [get_pins inst24[*]|d] 2.000
inst21 and inst 24 are registers. If this command is correct? If so, in which cases it works (both regs are clocked by the same clock and enable or clocks and enables could be different)? I tried it with different enables and common clk, and I got no error or warnings from TA, but from TA reports it's clear that requirement isn't met. At the same time TA doesn't indicate that requirement isn't met. If anybody is interested in such issue, my simple project is applied. - Altera_Forum--- Quote Start --- I meant that in my project mult has internal registers, which are clocked by fast_clk. OK, thank you, kaz. --- Quote End --- if you don't have enable on mults you can add it so that you use enable based sdc approach for multicycle. Otherwise it wouldn't do and you have to identify all paths in your multicycle sdc statements e.g all regs to mult and all regs from mult. Moreover you may have problem with sampling phase of result if you don't control that with enable.
