Timing requirements to a part of a circuit

the main approach is just to set a clock constraint with any multi-cycle constraints you require. If there are problems, fix the RTL.

If you then decide you cannot fiddle with the RTL any more, only then should you consider using logic lock regions. Only now when you have a few failing paths should you consider max_delay constraints. Going down this road is a lond and tedious one with lots of trial and error. Much easier to stick with clock constraints.