Timing requirements to a part of a circuit

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I meant that in my project mult has internal registers, which are clocked by fast_clk. OK, thank you, kaz.

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if you don't have enable on mults you can add it so that you use enable based sdc approach for multicycle. Otherwise it wouldn't do and you have to identify all paths in your multicycle sdc statements e.g all regs to mult and all regs from mult. Moreover you may have problem with sampling phase of result if you don't control that with enable.