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Honored Contributor
Honored ContributorTiming requirements to a part of a circuit
Does anybody know how to set timing requirements to a part of a circuit? I mean there is a critical part of a circuit that needs frequency optimization, and it's not rational to apply frequency cons...
Altera_ForumHonored Contributor
Honored Contributormax delay applies an absolute timing relationship, in nanoseconds between two nodes. It is NOT related to the clocks. If these are 2 registers and you already have clock constraints, then this max delay constraint is already infered at the clock delay. putting a max delay constraint of 2ns is like having a clock constraint of 500Mhz, so you are probably over-constraining the design.
This is NOT how you apply multicycle constraints.
