Timing requirements to a part of a circuit

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kaz, is it enough for a simple project just two lines for sdc file: create_clock -period 10.000 -waveform {0.000 5.000} -name fast_clk [get_ports {fast_clk}]

set_max_delay -from [get_pins inst21

[*]|q] -to [get_pins inst24

[*]|d] 20

?

If I use 2 ns instead of 20 there will be no timing error.

Thank you both for your support.

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Your path inst21 to inst24 is enabled once every two clocks so apply multicycle (if it is failing), not set max delay