Timing requirements to a part of a circuit

Tricky, fortunatelly, my project (I mean my real project, not example from the cookbook) works normally with current clk frequency (96 MHz - fast version and just 24 MHz - slow version). However, in some cases I use such chains like reg (clk,ena)->logic->reg (clk)->logic->reg(ena,clk). Here I use reg(clk) just to divide long logic chain into two parts (I guess it facilitates routing). Multicycle analysis isn't applicable here. TA warns me and shows negative slacks for such circuits, because it takes all these regs as regs(clk). What I do is control delays in this paths by myself and make sure that slacks are OK . Of, course, as long as my project works I'll not do any tedious work :) But I would like to study how to use TA because it's a useful thing.

kaz, is it enough for a simple project just two lines for sdc file: create_clock -period 10.000 -waveform {0.000 5.000} -name fast_clk [get_ports {fast_clk}]

set_max_delay -from [get_pins inst21

[*]|q] -to [get_pins inst24

[*]|d] 20

?

If I use 2 ns instead of 20 there will be no timing error.

Thank you both for your support.