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I'm just trying different possible approaches. That was my mistake when I used set_multicycle_path and set_max_delay at the same time. Yes, you are right, multicycle relaxes constraints. I'm thinking that in some situations we can use set max delay just to constraint one or several data paths rather then using multicycle together with clock constraint
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set_min_delay and set_max_delay:
These constraints can emulate multicycle constraints. set_max_delay overrides SMC and set_min_delay overrides HMC.
For example SMC of 2 and HMC of 1 means set_max_delay to 2 clock periods and set_min_delay to 0 clock period. However, delay values are in time units rather than clock periods and so can be defined with higher resolution.
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