I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.

Hi Sumanth,Thank you for your question. On the Cyclone 10 GX 10CX150YF672E5G, the Remote Update IP may not respond immediately after reset because the FPGA takes up to 830 µs to complete initialization and enter user mode (as specified in the datasheet). Accessing the IP before this time can cause issues.Recommendation:Wait at least 830 µs after reset, or use the INIT_DONE signal to confirm the device is ready, before interacting with the Remote Update IP. This timing can differ between device variants, so always follow the longer delay for compatibility. Let us know if you have any further questions.Regards,Fakhrul

For your information: The reset of the remote update IP is controlled by the lock signal from the PLL IP and is initiated after FPGA initialization.

In my design, I am giving reset for Remote Update IP based on lock signal from the PLL IP. Later trying to read the current configuration boot address.

Hi Sumanth, Thank you for sharing the details.Using the PLL lock signal for the Remote Update IP reset is a good approach, but please note that PLL lock does not guarantee the IP is ready. The FPGA may still be completing its initialization sequence, and the Remote Update IP needs additional time for its internal state machine to become ready.Recommendation:After releasing reset, poll the IP’s busy signal before reading the boot address. This ensures the IP is ready.Alternatively, use INIT_DONE or wait up to 830 µs after CONF_DONE for safe operation (per device datasheet). Regards,Fakhrul

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)

29 Replies

Sumanth
New Contributor
3 months ago
Thanks for the suggestions.

Related to the recommendation:
In my code it is already taken care to check IP's busy signal before doing any read operation.

During the reset, whether remote update IP will assert busy signal until initialization is complete?
Is there any other mechanism to know that remote update IP is ready?

Thank you.
FakhrulA_altera
Regular Contributor
3 months ago
Hi Sumanth,

Thank you for your question. On the Cyclone 10 GX 10CX150YF672E5G, the Remote Update IP may not respond immediately after reset because the FPGA takes up to 830 µs to complete initialization and enter user mode (as specified in the datasheet). Accessing the IP before this time can cause issues.

Recommendation:
Wait at least 830 µs after reset, or use the INIT_DONE signal to confirm the device is ready, before interacting with the Remote Update IP. This timing can differ between device variants, so always follow the longer delay for compatibility.

Let us know if you have any further questions.

Regards,
Fakhrul
- Sumanth
  New Contributor
  3 months ago
  For your information: The reset of the remote update IP is controlled by the lock signal from the PLL IP and is initiated after FPGA initialization.
  - Sumanth
    New Contributor
    3 months ago
    In my design, I am giving reset for Remote Update IP based on lock signal from the PLL IP. Later trying to read the current configuration boot address.
Farabi
Regular Contributor
3 months ago
FakhrulA_altera

Forum Discussion

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)

29 Replies

Recent Discussions

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Bidirectional differential port on MAX10

Quartus Pro invalid command name "End-trace"

GTS Transceiver Compatibility

Backplane Ethernet 10GBASE-KR PHY FPGA IP