New Contributor
Regular ContributorHi Sumanth,
Thank you for your question. On the Cyclone 10 GX 10CX150YF672E5G, the Remote Update IP may not respond immediately after reset because the FPGA takes up to 830 µs to complete initialization and enter user mode (as specified in the datasheet). Accessing the IP before this time can cause issues.
Recommendation:
Wait at least 830 µs after reset, or use the INIT_DONE signal to confirm the device is ready, before interacting with the Remote Update IP. This timing can differ between device variants, so always follow the longer delay for compatibility.
Let us know if you have any further questions.
Regards,
Fakhrul
New ContributorFor your information: The reset of the remote update IP is controlled by the lock signal from the PLL IP and is initiated after FPGA initialization.
New ContributorIn my design, I am giving reset for Remote Update IP based on lock signal from the PLL IP. Later trying to read the current configuration boot address.
Regular ContributorHi Sumanth,
Thank you for sharing the details.
Using the PLL lock signal for the Remote Update IP reset is a good approach, but please note that PLL lock does not guarantee the IP is ready. The FPGA may still be completing its initialization sequence, and the Remote Update IP needs additional time for its internal state machine to become ready.
Recommendation:
Regards,
Fakhrul
