New Contributor
New ContributorFor your information: The reset of the remote update IP is controlled by the lock signal from the PLL IP and is initiated after FPGA initialization.
New ContributorIn my design, I am giving reset for Remote Update IP based on lock signal from the PLL IP. Later trying to read the current configuration boot address.
Regular ContributorHi Sumanth,
Thank you for sharing the details.
Using the PLL lock signal for the Remote Update IP reset is a good approach, but please note that PLL lock does not guarantee the IP is ready. The FPGA may still be completing its initialization sequence, and the Remote Update IP needs additional time for its internal state machine to become ready.
Recommendation:
Regards,
Fakhrul
New ContributorThanks for the suggestions.
Related to the recommendation:
In my code it is already taken care to check IP's busy signal before doing any read operation.
During the reset, whether remote update IP will assert busy signal until initialization is complete?
Is there any other mechanism to know that remote update IP is ready?
Thank you.
Regular ContributorHi Sumanth,
From my understanding, yes, during reset and initialization, the Remote Update IP will assert busy. It stays high until the internal state machine completes setup and the IP is ready to accept transactions.
There’s no other direct signal from the IP to indicate readiness. The recommended method is to wait for busy to go low before issuing any read or write. You can refer to the Remote Update Intel® FPGA IP User Guide for more details
Best regards,
Fakhrul
