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Sumanth
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2 months ago

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)

I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I expe...
Configuration
Core Logic
Programmable Logic Device
Sumanth's avatar
Sumanth
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26 days ago

For your information: The reset of the remote update IP is controlled by the lock signal from the PLL IP and is initiated after FPGA initialization.

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Sumanth
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26 days ago

In my design, I am giving reset for Remote Update IP based on lock signal from the PLL IP. Later trying to read the current configuration boot address.