Hello, In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signals on the bus indicate Data or Address . As the logic is checking for the edges on WRN and ALE in a process, Quartus thinks they are clocks and gives timing errors: "WRN and ALE are clocks and they are not constrained". How do I solve this issue having known that WRN and ALE are not clocks?

Set the signals as false paths.

Yes, I had set false paths on them. But Timing analyzer report still shows these two signals as unconstrained clocks in the clock status summary. My Code: --somewhere in the architecture PROCESS ( ale, adbus )BEGIN IF ( ale'event AND ale = '0' ) THEN address <= adbus; END IF ;END PROCESS; PROCESS ( wrn, clearn, adbus )BEGIN IF clearn = '0' THEN data<= "0000000000000000" ; ELSIF ( wrn'event AND wrn = '1' ) THEN data <= adbus( 15 DOWNTO 0 ); END IF ; END PROCESS I am using the edges of ALE and WRN to identify if it is address or data on the adbus, and the tool thinks these are clocks. There are also warnings: Warning (332060): Node: wrn was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: ale was determined to be a clock but was found without an associated clock assignment.

You're coding them like clocks so the tool will think they're clocks. What do your false path constraints look like?

The false path constraints are as follows: set_false_path -from [get_ports WRN] set_false_path -from [get_ports ALE]

I think as long as you are using edges instead of logic levels for these control signals, the tool will still look at these as clocks. Is there a reason why you must do this and can't just turn these processes into combinatorial logic instead of registers?

Timing analysis error on Asynchronous control signals

23 Replies

sstrell
Super Contributor
4 years ago
If your code from 11/2/21 is still the same, you are still coding these signals like clocked processes instead of combinatorial logic. You should look at adjusting your code such that the signals no longer look like clock signals to the compiler.
- NShan12
  Occasional Contributor
  4 years ago
  Hello @sstrell ,
  
  Alright. Thank you very much for your support. This issue can now be closed.
SyafieqS
Super Contributor
4 years ago
We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
SyafieqS
Super Contributor
4 years ago
Hi Naveen,

Let me know if there is any update from previous reply?
Are you able to constrain the clocks?
- NShan12
  Occasional Contributor
  4 years ago
  Hello @SyafieqS , sorry for a delayed reply. Held up with too many topics.
  
  To replace false path to clock groups, I should first create clock constraints on WRN and ALE. This is as per Intel's example set clock groups constraint:
  
  But since ALE and WRN are just address latch and write enable signals they do not have a clock period. So, I do not know how to write a generate clock constraint on ALE and WRN.
  
  The below screenshot shows the behaviour of ALE and WRN during a bus write cycle:
  
  Thank you.
SyafieqS
Super Contributor
4 years ago
Hi Naveen,

Are the signal still being ignored if you change the constraint from set_false_path to set_clock_group? I noticed that this is a asynchronous control signals.
SyafieqS
Super Contributor
4 years ago
Hi Naveen,

Can you click on check timing report and see if there is no clock report. You can see details of the no clock ignored as the warning mentioned that. You can see the target node of the clock with reason.
- NShan12
  Occasional Contributor
  4 years ago
  Hello @SyafieqS ,
  
  Sorry for a late reply. I could not check with 21.1 STD.
  
  But with QP20.1.1 STD, I find these results:
  
  1. The two unconstrained clocks are ALE and WRN.
  
  2. The check timing report: I guess the number 75 indicates the total number of cells which are controlled by ALE and WRN .
SyafieqS
Super Contributor
4 years ago
Naveen,

Have you able to resolve this at your end?
SyafieqS
Super Contributor
4 years ago
I mean 21.1 STD version, the latest Quartus release.
SyafieqS
Super Contributor
4 years ago
Naveen,

May I know if there is any update/concern from my previous reply?
SyafieqS
Super Contributor
4 years ago
Hi Naveen,

Speaking of legacy, you must be using the snippet to previous Quartus. What Quartus you are using now and prior to this? Can you try to use latest release and see if there is clock warning?
- NShan12
  Occasional Contributor
  4 years ago
  Hi SyafieqS_Intel,
  
  I am using Quartus 20.1.1 Standard. All the information/code and screenshots I have shared are from the same version.
  
  The legacy design was developed in MAXPLUS II.
  
  Thank you.
SyafieqS
Super Contributor
4 years ago
Naveen,

If thats the case, my suggestion is to check Ignored Constrain Report in Timing Analyzer. I suspect that few clock constraint has been neglected for some reason. Once you identified it, make sure the clock is valid, you can use node finder and check the node if it exist.
- NShan12
  Occasional Contributor
  4 years ago
  Hello,
  
  I checked the ignored constraints report in Timing analyser. It shows no constraints are ignored. See screenshot below:
  
  But the warning: "Warning (332060): Node: WRN was determined to be a clock but was found without an associated clock assignment." still remains. Just to remind you, I am not using edges of WRN to latch data. I do not understand why WRN is considered as a clock even though I am not coding it as a clock.
  
  Thank you!